1. Field of the Invention
The present invention relates to a voltage boosting circuit for use in a semiconductor device such as a memory device.
2. Description of the Related Art
In a semiconductor memory using an NMOS transistor as a transfer gate, in order to turn on the NMOS transistor, whose gate electrode is connected to a long word line, at a high speed and to compensate a voltage drop at the NMOS transistor and on the word line, the voltage VOUT applied to the word line must be made higher than the power supply voltage VCC. For example, in a case where the power supply voltage VCC is 2V, the applied voltage VOUT is made to 4V. In order to generate this higher voltage VOUT, such a voltage boosting circuit 10 as shown in FIG. 8 is used.
In this circuit, the power supply voltage VCC is connected via diode 11 to an output line 12, and the boosted voltage VOUT is taken out from the output line 12. In a case where the power supply voltage VCC is more than 3 V, the voltage VOUT will be converted into a desired value by once pumping-up operation. However, if the power supply voltage VCC is less than 2V, twice or more pumping-up operations will be required. Therefore, pumping-up NMOS capacitors 13 and 14 are connected in series to the output line 12. Inverter 15 is connected via the NMOS transistor 16 to the node of a voltage VM between the NMOS capacitors 13 and 14, and a control signal *BIN is provided to the inverter 15. Herein, * denotes that the signal is active low. The output of a inversion delay circuit 17, constructed of inverters 17A through 17C connected in series, is connected to one end (voltage VE) of the NMOS capacitor 14, and the control signal *BIN is provided to the input of the inverter 17A.
FIG. 9 are time charts showing the operation of the circuit of FIG. 8.
In the initial state, the control signal *BIN is high, whereby the output of the inverter 15 is low, the NMOS transistor 16 is on, the output of inverter 17C goes low, and the voltages VM and VE each are 0V. In this state, the voltage of the NMOS capacitor 13 is VCC.
When the control signal *BIN turns to low, the output of the inverter 15 goes high, current from the inverter 15 flows to the NMOS transistor 16 to raise the voltage VM with the diode 11 being off, and when VM has reached to (VCC-Vth), the NMOS transistor 16 is turned off, where Vth is a threshold voltage of the NMOS transistor 16. Following up the rise of the voltage VM, the voltage VOUT is boosted. After the NMOS transistor 16 is turned off, namely the node of the voltage VM is in a floating state, the output of the inverter 17C turns to high, and the voltage VE is raised to VCC. Following up this, the voltages VM and VOUT are boosted.
A circuit which is similar to the above circuit and based on the same principle is disclosed in Japanese Laid-open Patent Publication No. 58-81325.
However, since the on-resistance of the NMOS transistor 16 becomes greater as the voltage VM approaches (VCC-Vth), the time period from the beginning of the output of the inverter 15 being high until the NMOS transistor 16 becoming off is relatively long. It is necessary that the voltage VE must be raised after the NMOS transistor 16 has turned off, therefore the rise time of the voltage VOUT by means of two-step boosting becomes longer. The rise time of the VOUT is, for example, 20 ns. Accordingly, speeding up memory access is prevented.